The invention relates to damascene processes in semiconductor wafer manufacture. In particular, the invention relates to chemical mechanical polishing (CMP) processes applied during damascene processes.
In the semiconductor industry, copper is replacing aluminium as a metal for forming conductive interconnects and bond pads in semiconductor wafers. This is because when compared to aluminium, copper has lower electrical impedance and higher electromigration resistivity. However, as there are no known conventional technologies for etching a copper pattern in the semiconductor industry, a conventional copper damascene technology is therefore used for forming copper conductive interconnects in wafers.
A conventional damascene process begins by the formation of a dielectric layer over a wafer substrate. The dielectric is patterned, for example using photolithography to form a photoresist layer for providing a mask for etching the dielectric. By etching, trenches are then formed in the dielectric which are defined on the sides by the dielectric and on the bottom by the substrate. A layer of conformal conductive material or metal such as copper is deposited over the patterned dielectric, whereby the trenches therein are filled. The wafer surface is then polished to achieve a substantially planar dielectric surface and remove any excess or residue conductive material or metal while leaving behind the conductive material or metal in the trenches in the patterned dielectric. In a copper damascene process, electrochemical plating of copper is applied to deposit a layer of copper over the dielectric pattern after which CMP processing is used to remove any excess or residue copper on the wafer surface.
Conventional abrasive CMP technologies are currently used in the semiconductor industry for forming a copper pattern in a wafer. A typical abrasive copper CMP process primarily includes a sequence of steps shown respectively in FIGS. 1 to 4. The first step involves the deposition of copper 102 over a conformal barrier layer 104 earlier deposited over a patterned dielectric layer 106 as shown in FIG. 1. The patterned dielectric layer 106 contains trenches 108 in which copper 102 is filled, which is defined at the bottom by the top of a substrate 110 upon which the dielectric 106 is based. The next step involves the removal of excess copper 102 above the plane of the dielectric 106 surface during a main polishing operation in which excess copper 102 detected by an end point detector is removed as shown in FIG. 2. This step, however, still leaves behind copper residues 202 forming mounds of copper and the underlying barrier layer 104 which lie above the plane of the surface of the dielectric layer 106. Therefore, an overpolishing operation is necessary to remove the copper residues 202 and barrier layer 104.
At the initial stage of the overpolishing operation, initial dishing or concavity 302 on the surfaces of the copper-filled trenches 108 begins to show, as shown in FIG. 3, even though some copper residues 202 still remain. However, the dishing problem worsens as severe dishing 402 arises when the overpolishing operation is completed at the end of the abrasive copper CMP process, which removes all copper residues 202 and the barrier layer 104 which previously lie above the plane of the dielectric surface as shown in FIG. 4. The severe dishing 402 which occurs at the end of the abrasive CMP process results in adverse consequences, affecting not only the resistance of copper conductive pattern, but also planarity of wafer which deteriorates subsequent lithography performance.
A conventional abrasive CMP process typically involves holding a wafer against a rotating wetted polishing pad surface under a controlled downward pressure. A polishing slurry such as a mixture of a chemical etch component and abrasive particles may be used. A rotating head or wafer carrier is typically used to hold the wafer under controlled pressure against a rotating polishing platen, which is typically covered with a polishing pad material for polishing the wafer.
A number of proposals are currently available for reducing dishing or concavity. Of particular note are proposals involving polishing slurries. In U.S. Pat. No. 5,607,718, a number of compounds are added to polishing slurry to decrease solution velocity thereby suppressing dishing. In U.S. Pat. No. 6,149,830, a viscosity modifier is added to polishing slurry to increase the viscosity of the polishing slurry for reducing dishing. In U.S. Pat. No. 5,770,095, a chemical agent is added to polishing slurry to form a protective film during CMP processing and to suppress the occurrence of dishing. In an article entitled xe2x80x9cslurry engineering for self-stopping, dishing free SiO2-CMPxe2x80x9d, IEDM, pages 349-352, 1996 IEEE, a surfactant is added to polishing slurry for obtaining global planarization.
Also notable are proposals relating to the rate of polishing during CMP processing. In U.S. Pat. No. 6,017,803, at least two metallic materials are deposited to form a damascene structure and the CMP process is used to remove the excess metals. No dishing occurs because there is control of the removal rates of different materials. In U.S. Pat. No. 5,618,381, a protective layer such as titanium is used before CMP processing, which may reduce dishing by controlling the removal rates of different materials.
Other proposals are also currently available for reducing dishing or concavity. Such proposals either involve improving polishing uniformity by improving polishing pad design or polishing pad material, or using a dummy structure for providing a more uniform slurry distribution.
Accordingly, there is a need for an alternative method for reducing dishing during CMP processing for addressing problems caused by dishing such as increasing the resistance of copper conductive patterns and reducing the planarity of wafers.
In accordance with a first aspect of the invention there is described a method for reducing dishing in a chemical mechanical polishing process performed on a semiconductor wafer having a dielectric layer with trenches and a copper layer deposited over the dielectric layer and filling the trenches in the dielectric layer. The method comprises steps of removing excess copper above the plane of the dielectric surface using a main polishing operation, whereby copper residues are formed above the plane of the dielectric surface, and applying chemical treatment to the surface of the semiconductor wafer in the initial stage of an overpolishing operation, wherein a protective layer over the copper residues and surfaces of copper-filled trenches is formed. The method further comprises steps of removing the copper residues and protective layer thereon above the plane of the dielectric layer in the overpolishing operation, and removing the protective layer over the surfaces of the copper-filled trenches in the overpolishing operation.
In accordance with a second aspect of the invention there is described in a method for reducing dishing in a chemical mechanical polishing process performed on a semiconductor wafer having a dielectric layer with trenches and a copper layer deposited over the dielectric layer and filling the trenches in the dielectric layer, the method comprising steps of removing excess copper above the plane of the dielectric surface using a main polishing operation, whereby copper residues are formed above the plane of the dielectric surface; applying chemical treatment to the surface of the semiconductor wafer in the initial stage of an overpolishing operation, wherein a protective layer over the copper residues and surfaces of copper-filled trenches is formed; removing the copper residues and protective layer thereon above the plane of the dielectric layer in the overpolishing operation; and removing the protective layer over the surfaces of the copper-filled trenches in the overpolishing operation, a chemical solution used for the chemical treatment, the chemical solution being introduced to the surface of the semiconductor wafer which reacts with the copper or is chemisorbed onto the surface of copper for forming the protective layer.